The present invention relates to an output circuit, and more particularly, to an output circuit for using in a circuit which is connected to a signal line, and which supplies signals to or receives signals from another circuit through the signal line.
A conventional output circuit of this type, for example, is used in a bus circuit. In the conventional bus circuit including the output circuits of this kind, a plurality of output circuits are connected to and asynchronously drive a common signal line. Each output circuit is controlled either in an enable state, in which a predetermined load driving current can be output, for communicating signals to another circuit through the common signal line, or in a disable state, in which no load driving current is output, for inhibiting communication of signals to another circuit through the common signal line. While only one output circuit is exclusively designated for occupying the common signal line, if the timing transferring from the enable state to the disable state is delayed in some output circuit, there will arise a bus fight that at least two output circuits are simultaneously in the enable state.
An example of output circuit to solve aforementioned problem is disclosed in the official gazette of Utility Model Laid-Open No. Sho 61-180342.
Referring to FIG. 33, the output circuit 1030 disclosed in the above gazette has a timing signal output circuit 1031, a delay circuit 1033 and a NAND gate 1036. The timing signal output circuit 1031 supplies a timing signal 1032 prescribing the bus enable timing. The delay circuit 1033 delays the timing signal 1032 outputted from the timing signal output circuit 1031 for a period td', and supplies a delay signal 1034 to the NAND gate 1036. The NAND gate 1036 inputs the timing signal 1032 supplied from the timing signal output circuit 1033 and the delay signal 1034 supplied from the delay circuit 1033, and supplies a bus occupation permit signal 1013 to a bus buffer 6. The bus occupation permit signal 1013 indicates the timing of switching the output of the bus buffer 6 from the disable to the enable state, or from the enable to the disable state.
As shown in FIG. 34, when the delay signal 1034 rises at the time delayed for the period td' from an enable timing T1' prescribed by a timing signal 1032, the output circuit 1030 asserts the bus occupation permit signal 1013. The period td' is the maximum value of the time from the timing which the bus occupation permit signal 1013 has transferred from the enable to the disable state to the timing which an output of the bus buffer 6 is transferred from the enable to the disable state. At the time T2', if the transfer from the enable to the disable state delays in the bus buffer 6, a bus fight does not occur. This is because the beginning of the next cycle is delayed for the period td'. In this conventional output circuit, the transfer of the bus buffer 6 from the enable to the disable state is intended to accomplish at a disable timing T2', which is prescribed by the timing signal 1032 supplied from the timing signal output circuit 1031.
The above-described conventional output circuit has the following problems.
First, there is a problem that an increase of signal propagation delay time causes a deterioration of an operation speed of the bus circuit. The reason is that, as shown in the timing chart of FIG. 34, the switching of the bus buffer 6 from the disable to the enable state is delayed by td' relative to the desired enable timing T1' prescribed by the timing signal 1032 supplied from the timing signal output circuit 1031.
Second, there is another problem that the transmission efficiency is deteriorated by increasing or the operation cycle time of the bus circuit. The reason is that, the delay by td' of the switching of the bus buffer 6 from the disable to the enable state also delays by td' the time by the transitional load driving circuit, generated on the common signal line of the bus circuit, to disappear. While this transitional load driving current is flowing, if the bus buffer 6 is switched from the enable to the disable state, so-called switching noise arises to distort signal waveforms on the common signal line of the bus circuit and possibly to invite data errors. Therefore, in the conventional output circuit, the switching of the bus buffer 6 from the enable to the disable state is delayed by td by delaying the disable timing T2' itself, prescribed by the timing signal 1032, and eventually the operating cycle time (T2'-T1') of the bus circuit is extended from the original cycle period by td.